1. Field of the Invention
The invention is directed to a monolithically integratable drive circuit with transmission circuits and an associated method for operating such a drive circuit to transmit an input signal such as from a drive logic unit to a driver.
2. Description of the Related Art
Drive circuits such as described herein are needed in power electronic systems to drive power semiconductor switches which are arranged as individual switches or in a bridge circuit. Such bridge circuits are known as single-phase, two-phase or three-phase bridge circuits in the form of power semiconductor modules. The single-phase so-called half-bridge constitutes the basic module of a multiplicity of power electronic circuits. In a half-bridge circuit, two power switches, a first so-called TOP switch and a second so-called BOT switch, are arranged in series.
Such a half-bridge generally has a connection to a DC intermediate circuit. The output, typically the AC voltage connection of the half-bridge, is usually connected to a load. The drive circuit generally consists of a plurality of partial circuits or function blocks. The control signal from a superordinate control logic unit, for example a microcontroller, is conditioned in a first partial circuit, the drive logic unit, and is supplied, via further components, to the driver circuits and finally to the control input of the respective power switch.
In the case of relatively high intermediate circuit voltages, generally greater than 40 V, the drive logic unit is usually isolated in terms of potential from the driver circuits, since the associated power switches are at a different potential and voltage isolation is therefore unavoidable. This isolation applies at least to the TOP switch, but is also embodied at higher powers for the BOT switch on account of possible chopping of the ground potential during switching. Such isolation can be realized, on the one hand, by DC isolation, for example by pulse transformers, optocouplers or optical waveguides, or, on the other hand, by integrated circuit technology, for example in an HVIC (High Voltage Integrated Circuit). The latter variant is being used with increasing frequency because it offers various advantages, such as small dimensions, low price and a long lifetime. In this respect, HVICs make it possible to integrate a high-voltage component with a breakdown voltage greater than or equal to the intermediate circuit voltage which can be used in circuits for signal level conversion, in so-called level shifters. A lateral high-voltage MOSFET is usually used for the latter.
Such a transmission circuit is part of the drive circuit and is preferably in the form of an integrated circuit arrangement. It serves for transmitting a signal from a circuit on the primary side having a defined reference potential to a circuit on the secondary side having an occasionally higher or lower reference potential. Bidirectional or unidirectional transmission circuits are known here.
Two basic isolation technologies are known for forming HVICs: firstly the SOI (Silicon On Insulator) technologies and secondly pn-isolated technologies (junction isolation). The SOI technology affords dielectric isolation of components and component groups, but is currently available only up to a dielectric strength of about 800 V. The SOI substrate wafers are significantly more expensive than standard substrates, although the costs are offset by a series of technical advantages and also considerable process simplifications which result from the dielectric isolation. In the case of pn-isolated technologies, the reverse voltage is taken up by a reverse-biased pn junction. This technology is currently available up to about 1200 V. However, production thereof is very complicated and therefore cost-intensive. Furthermore, there are technical problems, for example with leakage currents and latch-up effects, inter alia, at relatively high temperatures, for example at an operating temperature of more than about 125° C., and also in the event of chopping of the ground potential during fast dynamic operations.
In integrated drive circuits, the practice of transmitting the drive signals from the drive logic unit to the TOP secondary side associated with the TOP switch via level shifter circuits is known in principle according to the prior art. Driving with potential isolation is necessary, since the TOP secondary side, in contrast to the BOT secondary side associated with the BOT switch, is at an elevated reference potential in phases. According to the prior art of HVICs, signals are transmitted from the drive side to the TOP secondary side by pulsed (dynamic) differential transmission, switch-on and switch-off pulses being generated on the drive side from the signal to be transmitted and being transmitted to the TOP secondary side via a level shifter. This type of transmission is distinguished by a high degree of transmission reliability and a low power demand.
The most significant disadvantage of the method is the required generation of the switch-on and switch-off pulses. This results in increased circuit complexity and space requirement and thus higher costs. In principle, various integrated level shifter topologies are known. The simplest topology comprises an HV (high voltage) transistor having a corresponding blocking capability and a resistor in series. If a signal is passed to the gate of the HV transistor, the latter switches on. The shunt current thereby generated through the level shifter causes a voltage drop across the resistor, which can be detected as a signal by an evaluation circuit. By virtue of their principle, such level shifters with HV transistors contain a shunt current path, which is required for signal transmission, between the drive logic unit and the driver, and so no DC isolation is achieved.
DE 101 52 930 A1 discloses an improved level shifter topology in which the drive signal is transmitted progressively, by a plurality of identical level shifters connected in cascade, via intermediate potentials. It is thus possible to use transistors which have only a fraction of the required blocking capability of the entire level shifter. The blocking capability of the level shifter can thus be increased significantly.
DE 10 2006 037 336 discloses a level shifter in the form of a series circuit comprising n-channel HV transistors. This topology has the advantages that firstly the power consumption and secondly the circuit complexity are reduced by comparison with DE 101 52 930 A1. This results in a smaller space requirement and therefore also lower costs.
The common feature of all of these topologies for HVICs is that, in the case of complementary construction of the level shifter, it is also possible, in principle, to transmit signals from a circuit part having a high reference potential to a circuit part having a low reference potential. This property can be used to transmit signals back from the TOP secondary side to the drive logic unit. However, the prerequisite for this is a p-channel HV transistor.
Internal inductances of a system comprising a power semiconductor module and a drive circuit, for example line inductances, may result in severe chopping of the reference potential of the BOT secondary side in a positive or negative direction during switching of the power switches. Severe chopping of the reference potential of the TOP secondary side below the reference potential on the drive side may likewise result. This occurs to a particularly great extent in medium-power and high-power systems in which large currents, for example greater than 50 A, are switched. In this case, the potential difference can assume values that exceed the reverse voltage of the transistors used in the drive circuit, for example greater than about 20 V.
The known pn isolation technologies have the disadvantage that the triggering of parasitic thyristor structures, so-called latch-up, can occur in the event of corresponding chopping of the reference potential in the negative direction. This leads to loss of function and possibly to destruction of the affected transistors.
This limitation is not manifested in SOI technologies, due to the dielectric isolation of the components, with the result that it is possible to implement, using circuit technology, a level shifter which ensures reliable signal transmission even in the case of a secondary-side reference potential which is briefly or permanently negative. DE 10 2006 050 913 A1 discloses such a level shifter for the BOT secondary side embodied, using SOI technology, as an UP and a DOWN level shifter branch, while DE 10 2007 006 319 A1 discloses such a level shifter for the TOP secondary side embodied, likewise using SOI technology, as an UP and a DOWN level shifter branch.